PolarPAK^® Next Generation Packaging Technology for Power Hungry Applications

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As the power density requirements of DC-to-DC converters continue to increase, board real estate is becoming more critical, increasing the demand for power MOSFET packages with optimized footprint and improved thermal and electrical efficiency. Advances in silicon technology have helped to reduce on-resistance (RDS(on)) for a given die size to almost negligible levels. Now the MOSFET manufacturers have also increased their focus on new package options, allowing higher power density levels, while the silicon technology helps to reduce conduction losses and switching losses.

The SO8 package has been the default MOSFET package used in power hungry DC-to-DC converters and server applications because a combination of moderate on-resistance and gate charge has been seen as the optimal combination. Historically, the thermal conductivity of the SO8 packages offered an acceptable level of power dissipation. The resulting temperature rise was relatively low and could be accommodated within the design limits of the PCB. However, as the converters become smaller, the SO8 package footprint area began to occupy a relatively large part of the available PCB area for DC-to-DC converters. In addition, today's DC-to-DC converters can generate large amounts of power despite their small size. Therefore, maximum MosFET space utilization is critical.

 

PolarPAK^® A Unique Package Approach for Double Sided Cooling
Vishay Siliconix addressed this issue by developing a new surface mount package technology called PolarPAK. This patented package is low profile and thermally enhanced. It facilitates MOSFET heat removal from an exposed top metal lead frame connected to a drain surface in addition to a source lead frame connected to a PCB. It offers double sided cooling in an encapsulated plastic body occupying an SO8 footprint.

Fig.1: PolarPAK package and dimensions

 

The power loss in a DC-to-DC converter is a combination of conduction losses and switching losses. Maximizing the transfer of energy away from the MOSFET die will improve efficiency, since R_DS(on) is proportional to temperature. The relationship between die temperature and conduction loss can be described by the following equation:

 

Ts = C/(1-C/125)

Where

C = Rthja x I2 x RDS(on) (25°C) x K

K = Normalized variation of RDS(on) with temperature (typically around 1.8)

 

A power MOSFET generates internal heat due to the current passing through the channel. This self heating raises the junction temperature of the device above that of the PCB, to which it is mounted, causing significant increase in heat dissipation. Maximum efficiency in DC-to-DC converters can be achieved by selecting the appropriate package to carry out the switching application, reducing heat buildup in the die area by means of good thermal conductivity within the MOSFET, and effectively using board space with packages that can accommodate a large silicon area. Minimizing the increase in junction temperature will help to minimize the increase in die (silicon) temperature in power MOSFET package, hence increase the overall system efficiency.

The thermal simulation models use 2.5W of power and a 1” x 1” FR-4 double sided 0.062” thick PCB with 100% Cu on both sides. Vishay uses such a PCB for datasheet characterizations while specifying the R_th values. The temperature values in the pictures indicate the junction temperature for 2.5W at 25°C ambient. Thermal solutions such as airflow, a heat sink with no airflow and both heat sink and airflow were considered for these thermal simulations.

Fig. 2 compares the standard SOIC8 package and PolarPAK package at still air (no airflow) and without any heat sink. Under these conditions, the junction temperature (Tj) of the SOIC8 device is 448°C whereas that of PolarPAK is about 286°C. In other words, for the same footprint size the PolarPAK package provides a 162°C reduction in junction temperature when used instead of an SOIC8 package.

 

Fig. 2: Junction Temperature (Tj) comparision of SOIC8 and PolarPAK (in still air and without a heat sink)

 

As mentioned before, system performance can be improved when airflow and heat sinks are used. Fig. 3 shows the conditions where various airflows ((a)100-lfm; (b) 200-lfm; and (c) 400-lfm)) are used without any heat sink to optimize the power dissipation through the PCB as well as the topside of the package. At an applied power of 2.5W, the junction temperature for PolarPAK package is 255°C using 100-lfm and 225°C using 200-lfm. The junction temperature drops further to 207°C when a 400-lfm airflow is used. All of these conditions provide significant performance advantage compared to the Tj of an SOIC8 package. For example, under same load conditions, the junction temperature of an SOIC8 package with similar die size would be 448°C (using 100-lfm airflow), 367°C (using 200-lfm airflow) and 315°C (using 400-lfm airflow).

 

Fig. 3: Junction temperature under different airflow conditions

 

With the use of heat sinks and airflow, the PolarPAK package can perform even better by dissipating more heat out of the topside of the package. Using a 400-lfm airflow and a heat sink, the junction temperature for PolarPAK is reduced to 97°C.

 

Fig. 4 PolarPAK junction temperature with a 400-lfm airflow and a heat sink

 

Conclusion

By minimizing the thermal rise above the board temperature, the new PolarPAK packaging technology allows more heat to be dissipated from the MOSFWT, keeping on-resistance low and permitting the device to handle more current than any other SOIC8 type package. With its double-sided cooling, the PolarPAK package provides more than 75 percent reduction in junction temperature compared with a standard SOIC8 package while using 100-lfm airflow without any heat sink. Its performance can be further improved significantly when heat sink is used together with airflow.

PolarPAK was specifically designed for easy handling and mounting onto the PCB with high-speed assembly equipment and thus to enable high assembly yields in mass-volume production. This is one reason why PolarPAK has already earned the distinction of being the first MOSFET package with double-sided cooling to be sourced by multiple manufacturers.

The first PolarPAK power MOSFETs are the 30-V N-channel SiE802DF and SiE800DF. Optimized for the low-side control switch in synchronous rectification DC-to-DC converters, the SiE802DF offers exceptionally low on-resistance of 1.9 milliohms maximum at a 10-V gate drive (2.6 milliohms maximum at 4.5V) and can handle current levels up to 60A. The SiE800DF, optimized to work as the low-duty-cycle high-side MOSFET in synchronous DC-to-DC converter designs, features a very low typical gate charge Qg of 12 nC, with on-resistance of 7.2 milliohms maximum at 10V and 11.5 milliohms at 4.5V.

The new PolarPAK power MOSFETs, which have the same footprint dimensions of the standard SO-8, dissipate 1°C/W from their top surface and 1°C/W from their bottom surface. This provides a dual heat dissipation path that gives the devices twice the current density of the standard SO-8. With its improved junction-to-ambient thermal impedance, a PolarPAK power MOSFET can either handle more power or operate with a lower junction temperature. A lower junction temperature means a lower R_DS(on), which in turn means higher efficiency. A reduction in junction temperature of just 20°C can also result in a
2-½ times increase in lifetime reliability.

Typical applications for the new PolarPAK devices will include voltage regulator modules in notebook and desktop PCs, and other systems requiring high-efficiency DC-to-DC conversion. By delivering superior thermal performance and reducing package-related losses, the 5mm by 6mm PolarPAK package allows designers to create smaller, more compact circuit designs with a lower component count. With a height dimension of just 0.8mm, half the height of the SO-8, the PolarPAK package enables end products that are thinner as well.

Products built on TrenchFET Gen II technology are based on a 300-million-cells-per-square-inch platform offering a specific on-resistance of 12 milliohms per square mm, a 30% improvement over previous-generation silicon. In addition to its higher cell density, TrenchFET Gen II uses a new stripe topology that reduces mask count by 28%, optimizing turnaround and reducing costs.

 

Features First TrenchFET to break the 4-milliohm barrier at 4.5V in the SO-8 footprint Higher efficiency for reduced power consumption and prolonged battery life in end systems Extremely low Qgd/Qgs ratio provides substantial shoot-thru protection Reduce on-resistance and conduction losses further by allowing systems to run cooler Show a gain of nearly 1% in efficiency and a 7°C reduction in device temperature during testing in a typical application High-performing, cost-effective solution that simplifies manufacturing process

Applications DC/DC converters in notebook computers Synchronous rectification in fixed telecom power supplies

 

 

 Featured Products

Part Number		Description	Data Sheet	App. Notes
SIE800DF-T1-E3		N-Channel 30-V (D-S) MOSFET
SIE802DF-T1-E3		N-Channel 30-V (D-S) MOSFET
SIE806DF-T1-E3		N-Channel 30-V (D-S) MOSFET
SIE808DF-T1-E3		N-Channel 20-V (D-S) MOSFET
SIE810DF-T1-E3		TrenchFET Gen II Power MOSFET

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