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With over a decade of supporting industry standards such as PCI, PCI-X, PCI Express®, RapidIO®, VME and HyperTransport™, Tundra has developed a core competency in System Interconnect. Tundra’s products deliver the system performance and low power consumption customers need to reduce development time and risk, maximize system performance and accelerate time-to-market.

 

Tundra Host Bridges play a critical system role acting as a hub between the host processor, the system memory and the system input/output (I/O). The host processor and the system I/O both use the host bridge to access common system memory. In addition, the host processor uses the host bridge to configure and manage system I/O. Tundra offers host bridges that service high end discrete processors (the Tsi107™, Tsi108™, Tsi109™ and Tsi110™) as well as bridges that are architected more for embedded integrated controllers (QSpan™ II and PowerSpan™).

 

 

Tsi107

The Tundra Tsi107™ host bridge for PowerPC® provides system interconnect between PowerPC processors, PCI peripherals and local memory.

The Tsi107 processor interface supports Freescale and IBM PowerPC processors at frequencies up to 133MHz. It also supports a wide variety of system configurations by providing support for a second processor and a local slave device.

The PCI bus allows system designers to design systems quickly due to the vast number of PCI peripheral devices that are available. The Tsi107 PCI interface supports frequencies up to 66MHz and can operate as both a master and a target on the bus.

The Tsi107 provides many of the other necessities for embedded applications, including a high-performance memory controller and dual-processor support; two-channel flexible DMA controller; an interrupt controller; I²C controller; and low-skew clock drivers.

 

 

Clock Generation Cost Savings
The integrated clock generator of the Tsi107™ removes the need for external clock generation and buffering circuitry. Generation of these clocks can add significant costs to the overall system. These include not only the costs of the clock generators and buffers, but also the circuitry associated with these devices such as crystals and filtering components. Along with component costs come the routing constraints imposed by these additional devices.

 

 

PCB Cost Savings
The Tsi107 can reduce the space requirements necessary to implement a design and as a result save on PCB costs. There are several areas in which the Tsi107 saves space:

• The integrated clock generator of the Tsi107 removes the need for external clock generators and buffers. This reduces not only the space required for these external devices, but also the cost and power associated with these devices.
• The Tsi107 is offered in a 33mm x 33mm package
• The Tsi107 supports a 32-bit memory data path. If the 32-bit data path provides sufficient bandwidth for this application, it can result in significant space savings since only half the number of memory devices are required compared to a 64-bit implementation.

In addition, with a 1.27mm ball pitch and only 503 pins the routing requirements of the Tsi107 are minimal. This can result in a reduction in the number of PCB layers, further reducing cost.

 

 

Memory Cost Savings
The Tsi107 provides a flexible memory interface with support of a 64-bit or 32-bit data path. This can result in significant cost, power, and space savings since the memory system can be implemented with only half the number of memory devices (assuming a 32-bit data path can provide sufficient bandwidth for this application).

 

 

Performance
With a processor to memory latency of only 8 clock cycles, the Tsi107 offers the lowest memory latency of any PowerPC Host Bridge available today. Processor performance is often limited by memory latency, so the low latency of the Tsi107 can translate into increased performance. Because of the low latency, the Tsi107 is often used as the PowerPC companion chip during benchmarking of new processors from Freescale Semiconductor.

 

 

Processor Interface

• Supports the Freescale MPC603e, MPC7xx, and MPC74xx processors
• Supports the IBM PowerPC 603e, and PowerPC 7xx processors
• Processor bus frequency up to 133MHz
• I/O voltage: 2.5V or 3.3V
• SMP support for a second processor
• Full memory coherency, integrated arbiter and slave peripheral support

 

 

Memory Interface

• High-bandwidth (32-bit/64-bit) data bus up to 133MHz
• Programmable timing: supports either DRAM (FPM, EDO) or SDRAM Integrated SDRAM clock generation 8, 32, or 64-bit ROM/Flash ROM 8, 32, or 64-bit general-purpose I/O port: uses ROM controller interface with address strobe Supports parity, read-modify-write, or error-correcting code (ECC)

 

 

PCI Interface

• Compliant with PCI specification (revision 2.1)
• 32-bit PCI interface - up to 66MHz
• 5.0V compatible
• Integrated PCI Arbiter and Clock Generator

 

 

Other Features

• Two-channel integrated DMA controller
• Intelligent Input/Output (I²O) message controller
• Doorbell and messaging registers
• Inter-Integrated Circuit (I²C) Controller
• Embedded Programmable Interrupt Controller (EPIC)
• IEEE 1149.1 compliant, JTAG boundary-scan interface
• Power management unit

 

 

Block Diagram

 

 

Applications

The Tsi107™ may be used in a variety of embedded applications, which include the following:

• Routers
• Media gateway
• Network security
• Printers

A typical application diagram for the Tsi107 can be seen below:

 

 

 

Tsi108

The Tundra Tsi108™ is an advanced host bridge for PowerPC® processors that supports PCI-X, DDR2-400 SDRAM, Gigabit Ethernet, and Flash. The device contains numerous integrated features that enable customers to reduce system design complexity and system costs. As a result, the Tsi108 has the best price/benefits ratio on the market.

The Tsi108 builds on a decade of Tundra design experience in PowerPC host bridging. It delivers industry-leading performance for customers in the wireless infrastructure, storage networking, network access, printer, military, and industrial automation markets.

 

Lowers System Cost
The industry leading features and integration of the Tsi108™ allow system designers significant system cost savings versus other off-the-shelf host bridges. DDR2 support means memory costs are lower by as much as $20 as compared to using DDR. And the integrated Clock Generator with spread spectrum saves up to $10 versus using discrete devices with other host bridges. PCB costs are also lowered due to space savings resulting from feature integration, and the high reliability design can mean lower PCB costs. As well, the processor bus design at 200MHz can be implemented with only 8 layers with the MPC7448 or 750GX.

 

Lowers System Power
Aside from having the lowest power dissipation of any off-the-shelf host bridge, the Tsi108's support for DDR2 provides memory power savings of up to 50 percent when compared with DDR. The Tsi108 also minimizes active power by disabling unused ports and clocks, while its integrated Clock Generator saves power over discrete devices. The Tsi108 also conforms to the PCI Bus Power Management Interface Specification.

 

Superior System Performance
The advanced Switch Fabric architecture of the Tsi108 allows designers to significantly enhance system performance. The Ethernet Controller and PCI-X Interface offer superior data transfer rates. In addition, CPU to memory performance is exceptional due to features like configurable port arbitration priority and queuing reads ahead of writes.

 

Excellent Signal Integrity
The Tsi108's package was designed with reliability in mind. Flip-Chip packaging offers better electrical and thermal characteristics than wire bond packaged host bridges. VSS within I/O signals keeps I/O return current out of the core and is used as shields within the package to further reduce noise. VDD references within the memory and processor signals reduces coupling and noise from these high speed interfaces and keeps I/O current out of the core. The generous power and ground signals in a checkerboard pattern reduce the length of current loop between power and ground and provide the optimum pattern for effective decoupling. DDR2 support also offers superior signal integrity due to On Die Termination.

 

Integration
The Tsi108 feature set provides system designers with an array of integrated functionality to assist in lowering overall system cost, such as an integrated Clock Generator with spread-spectrum capabilities, a DDR2-400 Memory Controller, dual Gigabit Ethernet, and internal processor and PCI/X bus arbiters.

 

Configurability
Tsi108's flexible configuration options empower designers to develop their systems quickly and efficiently. Selection of PCI/PCI-X modes, an integrated Clock Generator, DDR2 support, and the ability to configure it as a PCI Host/Agent, all enable the Tsi108 to be used in a range of applications. The JTAG Interface also simplifies the debug process by allowing access to Tsi108's registers without impacting active transactions.

 

Applications
The Tundra Tsi108™ is an advanced host bridge for PowerPC processors that supports PCI-X, DDR2-400 SDRAM, Gigabit Ethernet, and Flash. The device contains numerous integrated features that enable customers to reduce system design complexity and system costs. As a result, the Tsi108 has the best price/benefits ratio on the market.

• Network access
• Industrial PC
• Multi-function printer
• Wireless infrastructure
• Industrial automation

 

 

Application Diagrams

 

Processor PMC

 

Industrial

 

Multi-function printer

 

 

 

Tsi109

The Tundra Tsi109™ is an evolution of the industry leading Tsi108 advanced host -bridge for PowerPC® processors. In addition to PCI-X, DDR2-400 SDRAM, Gigabit Ethernet, and Flash also found in the Tsi108, the Tsi109 also supports dual CPU operation, boasts an improved memory pipeline and offers integrated power management and industrial temperature operation. The Tsi109 is also pin and software compatible with the Tsi108 for those who want to boost performance in existing designs.

The Tsi109 builds on a decade of Tundra design experience in PowerPC host bridging. It delivers industry-leading performance for customers in the wireless infrastructure, storage networking, network access, printer, military, and industrial automation markets.

 

Superior System Performance
Dual processor support on the Tsi109™ allows designers to significantly enhance system performance in CPU intensive applications. Industry benchmarking proves the upgraded memory pipeline offers the best CPU to memory performance of any PowerPC host bridge. The Ethernet Controller and PCI-X Interface offer superior data transfer rates.

 

Lowers System Power
Aside from having the lowest power dissipation of any off-the-shelf host bridge, the Tsi109's support for DDR2 provides memory power savings of up to 50 percent when compared with DDR. The Tsi109 also minimizes active power by disabling unused ports and clocks, while its integrated Clock Generator saves power over discrete devices. The Tsi109 also conforms to the PCI Bus Power Management Interface Specification.

 

Lowers System Cost
The industry leading features and integration of the Tsi109 allow system designers significant system cost savings versus other off-the-shelf host bridges. DDR2 support means memory costs are lower by as much as $20 as compared to using DDR. And the integrated Clock Generator with spread spectrum saves up to $10 versus using discrete devices with other host bridges. PCB costs are also lowered due to space savings resulting from feature integration, and the high reliability design can mean lower PCB costs. As well, the processor bus design at 200MHz can be implemented with only 8 layers with the MPC7448 or 750GX. Integrated power management allows the processor, memory and PCI/X devices to be powered down in idle modes – key for printers and other consumer appliances.

 

Configurability
Tsi109's flexible configuration options empower designers to develop their systems quickly and efficiently. Single or dual CPU operation, selection of PCI/PCI-X modes, an integrated Clock Generator, DDR2 support, and the ability to configure it as a PCI Host/Agent, all enable the Tsi109 to be used in a range of applications. The JTAG Interface also simplifies the debug process by allowing access to Tsi109's registers without impacting active transactions.

 

Excellent Signal Integrity
The Tsi109's package was designed with reliability in mind. Flip-Chip packaging offers better electrical and thermal characteristics than wire bond packaged host bridges. VSS within I/O signals keeps I/O return current out of the core and is used as shields within the package to further reduce noise. VDD references within the memory and processor signals reduces coupling and noise from these high speed interfaces and keeps I/O current out of the core. The generous power and ground signals in a checkerboard pattern reduce the length of current loop between power and ground and provide the optimum pattern for effective decoupling. DDR2 support also offers superior signal integrity due to On Die Termination.

 

Integration
The Tsi109 feature set provides system designers with an array of integrated functionality to assist in lowering overall system power and cost, such as an integrated Clock Generator with spread-spectrum capabilities, a DDR2-400 Memory Controller, dual Gigabit Ethernet, power management, and internal processor and PCI/X bus arbiters.

 

Applications
The Tundra Tsi109™ is an advanced host bridge for PowerPC® processors that supports PCI-X, DDR2-400 SDRAM, Gigabit Ethernet, and Flash. The device contains numerous integrated features that enable customers to reduce system design complexity and system costs. As a result, the Tsi109 has the best price/benefits ratio on the market.

 

Applications

• Network access
• Blade server
• Industrial PC
• Multi-function printer
• Wireless infrastructure
• Industrial automation

 

 

Application Diagrams

 

Dual Processor PMC

 

Blade server

 

Industrial PC

 

 

 

Tsi564A

The Tsi564A™ is part of Tundra's family of second-generation RapidIO switches. Supporting 40Gb/s aggregate bandwidth, the Tsi564 enables customers to develop high-performance systems at low cost. The Tsi564 is targeted at chip to chip DSP and processor aggregation and comes in a small 21mm x 21mm package size. It is ideally suited for applications where power, cost and board space are primary concerns.

Using the Tsi564 flexible port configurations can be selected through multiple port width and speed options. The Tsi564 can be configured as a 8-port x1 switch or an 4-port x4 switch (or various combinations of x1 and x4). Each of the ports can be run at 1.25 Gbaud, 2.5 Gbaud or 3.125 Gbaud.

With a smaller footprint than the Tsi568ATM, the Tsi564A offers low power, multiple port-widths and speed configurations, making it ideally suited for applications where power, cost and board space are primary concerns.

Based on the Serial RapidIO Specification, the Tsi564A incorporates SerDes functionality, error recovery, priority-based fabric routing, high payload efficiency, and table-based fabric packet routing. In addition, the Tsi564A supports RapidFabric extensions including data streaming packet switching for interworking and encapsulation.

The device goes beyond standard specification requirements to solve system level issues with low power consumption, and hot swappable I/Os. The extensive buffering and traffic management architecture is specifically designed for line rate termination and the prevention of head-of-line blocking.

 

Improves Overall System Performance:

• Easy implementation of distributed processing between DSPs in clusters
• Free up DSPs resources for actual application processing vs. terminating protocol stacks in software
• Superior real time image processing resolution, size and frames per second in military and medical imaging systems
• Configurability provides more product variants per development dollar

 

Power

• Tunable power per port to optimize budget for application. With competing synchronous switches all ports must operate at the frequency of the highest speed port resulting in higher power dissipation
• Provides more processing power-per-watt through distributed processing

 

Applications
The Tsi564A™ supports embedded interconnect in a variety of applications, supporting connectivity at the board, backplane and chassis level.

• Wireless Base Station: Node B and RNC
• Video head end
• VOIP and media gateways
• Wireline networking
• Medical imaging
• Military image and signal processing

 

 

 

 

 

 

 

 

Tsi568A

The Tsi568A™ is Tundra's second-generation RapidIO switch. Supporting 80 Gb/s aggregate bandwidth, the Tsi568 enables customers to develop high-performance systems at low cost. The Tsi568 is targeted at:

• Chip to chip DSP and processor aggregation
• Board to board backplane interconnect
• Chassis to chassis interconnect over copper or optics

Using the Tsi568A flexible port configurations can be selected through multiple port width and speed options. The Tsi568 can be configured as a 16-port x1 switch or an 8-port x4 switch (or various combinations of x1 and x4). Each of the ports can be run at 1.25 Gbaud, 2.5 Gbaud or 3.125 Gbaud.

The Tsi568A supports open architectural standards such as AdvancedTCA and VITA VXS.

Based on the Serial RapidIO Specification, the Tsi568A incorporates SerDes functionality, error recovery, priority-based fabric routing, high payload efficiency, and table-based fabric packet routing. In addition, the Tsi568A supports RapidFabric extensions including data streaming packet switching for interworking and encapsulation.

The device goes beyond standard specification requirements to solve system level issues by optimizing performance, lowering power consumption, and supporting hot swappable I/Os. The extensive buffering and traffic management architecture is specifically designed for line rate termination and the prevention of head-of-line blocking.

 

Improves Overall System Performance:

• Easy implementation of distributed processing between DSPs in clusters
• Free up DSPs resources for actual application processing vs. terminating protocol stacks in software
• Superior real time image processing resolution, size and frames per second in military and medical imaging systems

 

Reduced Power Dissipation

• Tunable power per port to optimize budget for application. With competing synchronous switches all ports must operate at the frequency of the highest speed port resulting in higher power dissipation.

 

Applications
The Tsi568A™ supports embedded interconnect in a variety of applications, supporting connectivity at the board, backplane and chassis level.

• Wireless Base Station: Node B and RNC
• Video head end
• VOIP and media gateways
• Wireline networking
• Medical imaging
• Military image and signal processing
• ATCA and MicroTCA

 

 

 

 

 

 

 

 

 

 

Tsi148

The Tundra Tsi148™ is the highest bandwidth VME bridge available, providing PCI-X-to-VME 2eSST performance levels while maintaining backwards compatibility with older standards.

As the VME chassis continues to evolve, Tsi148 provides the bandwidth required to connect together distributed computing elements. VME systems are using distributed processing elements like CPUs, NPUs, and DSPs in order to manage the thermal density and provide scalability. New standards like VXS and VPX are using RapidIO® bus as the data path but in parallel VME bus traffic will also increase because control plane bandwidth scales with data bandwidth.

Tsi148's decoupled architecture and proper buffer sizing allows a very large number of simultaneous transactions to take place. Tsi148 is also a full featured master, slave and system controller which allows it to be used in any VME application. Its low power and small package size make it an ideal choice where space and power are concerns.

 

Industry's Highest Bandwidth
Able to sustain speeds of 305MB/s on the VMEbus, the Tsi148™ allows customers to build and connect together a more powerful system without experiencing a bottleneck to communication between cards.

 

Multi-threading
Being capable of simultaneous transactions means that overall system performance improves as neither bus is left waiting for transactions to complete. In addition to handling simultaneous transactions, large internal FIFO buffers help prevent the classic deadlock conditions that can arise in PCI/X to VME bridges. Further, Tsi148's dual independent DMA controllers support both direct and link-list modes and allow transfer sizes from 1byte to 4Gbytes to be executed. DMA transactions can follow any combination of the PCI and VME paths.

 

Lowest Power
Of course total power consumed depends on how the bus is loaded and how much data is passing through it, but Tsi148 has the lowest power of any VME bridge chip on the market and is nearly half the power of the popular Universe VME bridge chip.

 

Backwards Compatibility
Customers can upgrade a card at a time and see system benefits as the 2eSST transaction speed can take place along with the traditional VME64 transactions.

 

Flexible Interfaces
The Tsi148 supports all legacy protocols on both sides of the bridge. Specifically these are;

• All VME protocols (VME64, 2eVME, 2eSST) 64-bit data and 32- or 64-bit addressing. A full suite of addressing and data modes is implemented, including BLT and MBLT support.
• All PCI protocols. PCI from 33 to 66MHz and PCI-X from 50 to 133MHz. The Tsi148 has a 64-bit data path but can function in a 32-bit system as well. In PCI-X mode, the Tsi148 will support 2 loads thus reducing the need for additional PCI-X bridges.

Applications
In all applications, Tsi148 provides the bridge from any version of PCI local board interconnect to the VME backplane bus. Typical VME applications include;

• Single Board Computing card (see below)
• VXS Blade (eg. Compute node card, see below)
• VPX Blade (eg. Compute node card)

Single Board Computer – a self contained processing card with memory, processors and additional functionality via mezzanine (XMC) cards. Here the Tsi148 provides connection to the VME backplane bus which is then often connecting to peripheral devices.

 

 

 

VXS (VMEbus Switched Serial, VITA 41) Compute Node Card – In this application Tsi148 provides connection to the VME backplane bus through traditional VME connectors and a hi-speed connector (PO) is added for serial RapidIO data. This architecture allows multiple computing "blades" to plug into a backplane thus distributing the power within a system chassis and enabling scalable systems. The RapidIO serial data connection enables distributed computing because it provides a low latency connection between cards along with appropriate quality of service (QoS) features like error management. It also enables scalability because individual cards can be swapped in to add performance as required. In addition, the point to point connection nature of RapidIO means new cards can be swapped in live (hot swap). The Tsi148 provides the bandwidth required to keep up with these state-of-the-art computing platforms used for graphical and data processing intensive applications like Radar or Medical imaging.

 

 

 

 Featured Products

Part Number		Description	Data Sheet	App. Notes
TSI107C-100JE		Host Bridge for PowerPC®
TSI108-200CL		Host Bridge for PowerPC®
TSI109-200CL		Host Bridge for PowerPC®
TSI148-133CL		PCI/X-to-VME Bridge
TSI564A-10GCL		8/4 Port Serial Rapid IO Switch supporting V1.2 of the RTA Standard
TSI568A-10GCL		16/8  Port Serial Rapid IO Switch supporting V1.2 of the RTA Standard

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