Bridging the Wireless Divide

By Ralf Lehman

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The advantages of wireless communications are moving from the consumer sector to the industrial. But in this cost sensitive domain, engineers want to retain the existing processor hardware. This article explains how to bridge from 802.11x modules to legacy processors.

READ THIS TO LEARN ABOUT A flexible, cost effective means to bridge between Wi-Fi chipsets and legacy processors The characteristics of QuickLogic's QuickPCI device, and the design constraints the engineer should consider when using it

Wireless remote monitoring promises to transform the industrial landscape. Operating costs can be reduced and productivity enhanced by remote monitoring across an RF based network. However, extending 802.11a/b/g (widely known by the proprietary name, Wi-Fi) to the industrial sector, relies on cost sensitive implementation. In most cases, the project's justification depends on retaining the existing network processing and switching hardware. Unfortunately, these devices were never designed to interface directly with Wi-Fi modules, making the designer's life much more challenging.

The semiconductor vendors are trying to help by adding wireless-friendly interfaces - such as the computer world's PCI, and the consumer motivated SDIO to their chips. Unfortunately, commercial quantities of these devices are unlikely to be available for at least 12 months. Finding a short term solution is appealing, because it will give progressive designers an opportunity to differentiate their industrial network by adding a Wi-Fi capability to their control or monitoring product. And this short term solution comes in the form of a bridging device, capable of controlling, buffering and arbitrating communications between the wireless module and the legacy processor. This bridge device allows companies to continue to use the substantial investment they have made in their original hardware, software and Intellectual Property (IP).

A typical bridging device is available from QuickLogic. This chip has an added advantage in that it features an FPGA-based programmable fabric, allowing extra design flexibility. But how easy is it to implement a Wi-Fi enabled network using given processors and a bridging device? Well, much depends on the performance of that processor, the bus bandwidth and the software latency. In this article, we will take a look at a couple of examples which will illustrate the process using hardware available from Future Electronics.

 

Wireless Moves In
802.11a/b/g has been established as the most popular standard for wireless data transfer. Originally designed for portable personal computers, Wi-Fi, as it is more commonly known, is rapidly moving into other application areas, particularly the industrial sector where the benefits are huge.

The predominant interface for Wi-Fi chipsets currently on the market is the PCI bus, the standard bus employed in PCs. In portable or embedded applications, PCI is usually based on the same signalling but a different form factor. Note that since 802.11a/b/g chipsets have originally been built for a PC environment, drivers for a different architecture are usually not available from the vendors of the wireless devices. This means the designer will need to create custom drivers.

While newer embedded microprocessors frequently have an integrated PCI interface that allows easy connection to standard 802.11a/b/g chipsets, many legacy and low cost processors do not. Instead, they support a processor, specific local bus or a simple memory interface (for example, SDRAM).

Unfortunately, there are currently no 802.11a/b/g chips available that can directly interface to these processor specific local buses. Consequently, to add wireless connectivity to a system with a legacy processor, the bridge device is required. Selecting the appropriate bridge depends on the available interfaces and required bandwidth.

Of the major semiconductor companies, QuickLogic is the most notable for bridging chips. These are suited for portable wireless applications because they feature the low power consumption essential to portable devices. The company has also introduced a range of devices that include FPGA architecture (Eclipse II and QuickPCI).

QuickLogic QuickPCI devices contain a fixed function PCI core embedded in a programmable fabric. The programmable fabric provides the flexibility necessary to bridge between different local bus architectures and the embedded PCI core.

 

Building a Direct Bridge
The simplest way to connect a processor to a bridging device is via the processor's local bus. The hardware implementation is relatively straight-forward but can cause data bottlenecks, as demonstrated in this first example. Figure 1 illustrates a direct bridge implementation with QuickLogic's QL5822 QuickPCI device.

 

 

If the local processor bus supports an external device to master the bus and write data directly into the processor's memory, the bridge can forward any Direct Memory Access (DMA) transfer executed by the wireless chipset to this external system memory. However, many embedded processors do not support this type of direct access to the main memory. To get the data in and out of these devices, the processor must read or write on the local bus.

Since the 802.11a/b/g chipsets are built to support DMA on the PCI bus, the bridge would need to be configured as a bi-directional buffer device allowing the wireless chipset to access the buffer via PCI DMA, while the processor accesses the bridge's other side via the processor's local bus protocol. However, to synchronize the local bus and PCI bus data streams, data must be buffered within the bridge device. The bottleneck mentioned earlier can occur if there is a mismatch between the size of the buffer RAM within the PCI bridge device and the latency between a request for a transfer on the local bus and the execution by the processor.

The choice of bridging device RAM allocation is determined by bandwidth requirement of the wireless application, and bus latency dictated by the software (for example, the interrupt response time). Table 1 lists typical wireless applications and their bandwidth requirements.

 

Applications	Payload Bandwidth (bps)	Payload Bandwidth (byte/sec) (kbit/s)
MPEG2 Video	9.8M	1.225M
MPEG4	2.254M	281.8K
MPEG4-AVC/H.264 Video	1M	128K
5-Channel Audio	320K	40K
MP3 (Stereo and CD Quality)	128K	16K
ISDN (Per B Channel)	64K	8K
AVI Video Streaming	64K	8K

 

QuickLogic offers bridging options that can be tailored to bandwidth requirements and processor latency time. The first and most straightforward option is a design based on a QL5822 QuickPCI device programmed with a local interface. If the bandwidth and latency requires more buffer in the bridging device, external SRAM can be added. If the application requires modest bandwidth or the microprocessor has a fast response, a less expensive QL8050 using a customized PCI is the answer. Figure 2 shows the maximum latency for a selection of bridging devices.

 

 

While some processors do not allow an external device to master the bus and write data directly into the processor memory, they do support external mastering of SDRAM. For these processors the bridge works in a different way. The processor and SDRAM buses are both connected to the bridge. The hardware implementation is more complicated since the SDRAM bus is now connected to an additional device and the bridge must support the SDRAM access protocol. However, this architecture has several advantages over the previous design. Figure 3 shows a typical set-up.

 

 

Firstly, the wireless driver implementation is easier because the set-up mirrors common PC architecture. The 802.11a/b/g chipset can transfer data using DMA via the transparent bridge directly into the main memory of the processor. Consequently, standard PC software drivers can be reused without major modifications.

Secondly, the processor is not burdened with handling data packets transferred in and out of the bridge buffer. All basic data transfers are handled by hardware so interrupt response time or stacking of interrupts is not a concern. Finally, buffer size is not critical, since the bridge delays any PCI transaction until the SDRAM bus is available. Delays on the PCI bus have no impact on throughput since the maximum 802.11a/b/g bandwidth of 54Mbit/s is much smaller than PCI's bandwidth of 132Mbit/s. In my experience, this second option is the best for all processors that support external mastering of the SDRAM bus.

 

A practical implementation
Let us consider a practical example using a ColdFire™ device from Freescale Semiconductor. The section below "Inside the ColdFire Process" details the MCF527x ColdFire specification.

The MCF527x has a DMA Controller (DMAC) that provides an effective way to move blocks of data with minimal processor interaction. The DMA module provides four channels that allow byte, word or long word operand transfers. These transfers can be single or dual address to off-chip devices or dual address to on-chip devices. By using one of the external request pins (DREQ[3:0]), the QL5822 can work transparently, as described in the second bridge implementation above.

 

 

Figure 4 illustrates the basic system block diagram integrating wireless connectivity to the MCF527x processor. The sideband SRAM is an option to increase DMA performance as detailed in the second example above. The ColdFire processor serves as the host processor that configures and manages the system. Upon boot-up, the processor can initiate configuration cycles through the QuickLogic device to enumerate the miniPCI bus and configure the WLAN chipset. The QuickPCI device operates as the host miniPCI bridge with a built-in arbiter.

The QL5822 QuickPCI chip implements the bridge between the MCF527x and the Wi-Fi module. Figure 5 shows the internal structure of the device.

 

 

Wi-Fi traffic is written to the shared SRAM buffer via miniPCI through the QuickLogic bridge. Likewise, Wi-Fi traffic is read from the SRAM buffer via miniPCI through the QuickLogic bridge. Once packets are written or read, the QuickLogic bridge can interrupt the processor to read from, or write to, the SRAM.

The section below, "QL5822 Internal Structure" describes the elements of the chip in more detail. One interface of special note – which owes its existence to QuickLogic's Embedded Standard Products (ESP) range that offers interfaces other than PCI – is SDIO. Driven by the PDA and smartphone market, this allows Wi-Fi functionality to be added to handheld devices.

By implementing an SDIO interface in a similar way to PCI, it is possible to provide industrial applications with Wi-Fi functionality by using a COTS card.

 

Protecting Investment
Industrial electronics engineers are under pressure to realize the benefits of wireless networking without sacrificing the previous investment in capable processors although lacking wireless compatible interfaces.

However, this challenge can be eased by employing bridging devices that can interface to the wireless module and the processor. QuickLogic, for example, offers several custom solutions that can bridge an 802.11a/b/g PCI device to a legacy microprocessor. The programmable fabric of QuickLogic devices provides bridging between any microprocessor device with a generic local bus and a PCI 802.11a/b/g device.

Care must be taken though, because the processor performance and architecture need to be matched to the bridging chip and the high data transfer rate of Wi-Fi. Expert advice on the optimum choice of hardware can be sought from Future Electronics. The company can offer a level of impartiality in recommended solutions that few other distributors have the breadth and diversity of product range to match. Future can also offer full technical expertise and guidance in all aspects of wireless network implementation.

 

 

Inside the Coldfire Process The MCF5275 family is a highly integrated implementation of the ColdFire family of RISC microprocessors. It provides 144MIPS at 150MHz (Dhrystone 2.1). ColdFire devices are suitable for cost sensitive applications requiring significant control processing for file management, connectivity, data buffering and signal processing. The devices suit a variety of markets including industrial control, security, imaging and medical. Figure A shows the integrated modules of an MCF5275. Features ColdFire Version 2 Core with Enhanced Multiply-Accumulate Unit (EMAC) Up to 150MHz system clock 16kByte Instruction/Data cache 64kByte SRAM 2 interrupt controllers 4 channel DMA DDR SDRAM controller Up to two fast Ethernet controllers USB device module 4 x 32-bit DMA timers QSPI and three UARTs 4 PWMs General purpose I/O module Cryptography – security module on some devices Debug BDM Figure A   Inside the Coldfire Process – View the ColdFire course (80MB Zipped Download)

 

 

QL5822 Internal Structure PCI Core A 32-bit/33MHz host/master/target core that interfaces between the PCI bus interface block and the PCI bus that is connected to the 802.11a/b/g chipset.   Host Interface The interface communicates with the Enhanced Interface Module (EIM) of the MCF527x via DMA transfers, decodes the local address of the transfers and steers the transaction to/from the SRAM, the control/status registers and the PCI bus interface.   The PCI Arbiter This device is responsible for arbitrating the PCI bus master between the Wi-Fi module and the QL5822 bridging chip.   PCI Configuration Header This decodes address information during PCI accesses.   PCI Bus Interface The PCI bus interface communicates with the PCI core. The host interface communicates with the PCI bus interface to perform the required transaction on the PCI bus. The PCI bus interface is also responsible for making the SRAM available to accesses from the 802.11a/b/g chipset.   SRAM Interface (option) The interface communicates with the SRAM device and arbitrates concurrent accesses from the PCI and the host. It is used for temporary storage of data between the processor and the Wi-Fi module. This is an option for increasing the performance for DMA transfers and increases the latency budget. If the built-in memory of the QL5822 fulfils the bandwidth demands this module is not required.   Control/Status Registers The control/status registers are accessible from the host interface block to provide control/status information for the local processor. It also manages the power scheme/modes of the Wi-Fi module and bridge device.