EXcyte™ SONET/SDH PHY Family

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XRT91L30 - STS-12/STM-4 OR STS-3/STM-1 SONET/SDH Transceiver

The XRT91L30 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08Mbps STS-12/STM-4 or 155.52Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the high speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The internal CDR unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. Either the internally recovered clock or the externally recovered clock can be used for loop timing applications. The chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide LVTTL system interface in both receive and transmit directions.

The transmit section includes an 8 x 9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, the FIFO can automatically recover from an overflow condition. The device can monitor Loss of Signal (LOS) condition and automatically mute received data upon LOS. An on-chip SONET/SDH frame byte and boundary detector and frame pulse generator offers the ability to recover SONET/SDH framing and to byte align the received serial data stream into the 8-bit parallel bus.

 

FEATURES Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 applications Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08Mbps or STS-3/STM-1 155.52Mbps Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit Ability to disable and bypass on-chip CDR for external based received reference clock recovery thru Differential LVPECL input pins XRXCLKIP/N 8-bit LVTTL parallel data bus paths running at 77.76Mbps in STS-12/STM-4 or 19.44Mbps in STS-3/STM-1 mode of operation Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44MHz or 77.76MHz for both STS-12/STM-1 or STS-3/STM-1 operations Optional use of 77.76MHz Single-Ended LVTTL input for independent CDR reference clock operation Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus Diagnostics features include LOS monitoring and automatic received data mute upon LOS Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode Optional access to internal FIFO has the advantage of permitting the upstream device time domain to be decoupled from the transceiver transmit timing and re-configure the transmit parallel bus clock output to a clock input and accept timing signal from the upstream device Meets Telcordia, ANSI, Bellcore TR-NWT-000253 and GR-253-CORE, and ITU-T jitter requirements Operates at 3.3V with 3.3V I/O Less than 660mW typical power dissipation Package: 10 x 10 x 2.0mm 64-pin QFP

APPLICATIONS SONET/SDH-based transmission systems Add/Drop multiplexers Cross connect equipment ATM and multi-service switches, routers and switch/rRouters DSLAMS SONET/SDH test equipment DWDM termination equipment

 

 

XRT91L80 - OC-48/STM-16 SONET/SDH Transceiver (2.488/2.666Gbps)

The XRT91L80 is a fully integrated SONET/SDH transceiver for SONET OC-48 allowing the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the high speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream.

The chip provides serial-to-parallel and parallel-to-serial converters and 4-bit LVDS system interfaces in both receive and transmit directions. The transmit section includes a 4 x 9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter input clock and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section.

 

FEATURES Single chip fully integrated solution Low power (400mW) Host Mode support Separate reference and VCXO input ports On-chip phase detector and charge pump Low Jitter performance

APPLICATIONS SONET/SDH based transmission systems Add/Drop multiplexers Cross connect equipment ATM and multi-service switches Routers, switch/router combinations SONET/SDH test equipment DSLAMs DWDM termination equipment

 

 

XRT91L82 - 2.488/2.666GBPS STS-48/STM-16 SONET/SDH Transceiver

The XRT91L82 is a fully integrated SONET/SDH transceiver for OC-48/STM16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the high speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions. The transmit section includes a 16 x 9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section.

 

FEATURES 2.488/2.666Gbps transceiver Targeted for SONET OC-48/SDH STM-16 applications Selectable full duplex operation between standard rate of 2.488Gbps or Forward Error Correction rate of 2.666Gbps Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial to-parallel converter and clock data recovery (CDR) functions 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL signaling data paths running at 155.52/166.63Mbps using internal input termination for reduced passive components on board Non-FEC and FEC rate REF1CLKP/N and REF2CLKP/N dual reference input ports Supports 155.52/166.63MHz or 77.76/83.31MHz transmit and receive external reference input ports Optional VCXO input port support multiple de-jittering modes in Host mode On-chip phase detector and charge pump for external VCXO based de-jittering PLL Internal FIFO decouples transmit parallel clock input and transmit parallel clock output Provides Local, Remote Serial and Remote Parallel Loopback modes as well as Loop Timing mode Diagnostics features include various lock detect functions and transmit CMU and receive CDR Lock Detect Host mode serial microprocessor interface simplifies monitor and control Meets Telcordia, ANSI and ITU-T jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, GR-253 CORE, GR-253-ILR- SONET Jitter specifications Operates at 1.8V CMOS and CML Power with 3.3V I/O 500mW typical power dissipation using LVDS interface Package: 15 x 15mm 196-pin STBGA IEEE 1149.1 Compatible JTAG port

APPLICATIONS SONET/SDH-based transmission systems Add/Drop multiplexers Cross connect equipment ATM and multi-service switches, routers and switch/routers DSLAMS SONET/SDH test equipment DWDM termination equipment

 

 

 Featured Products

Part Number		Description	Data Sheet	App. Notes
XRT91L30IQ-F		STS-12/STM-4 or STS-3/STM-1 SONET/SDH Transceiver
XRT91L31IQ-F		STS-12/STM-4 or STS-3/STM-1 SONET/SDH Transceiver
XRT91L32IQ-F		STS-12/STM-4 or STS-3/STM-1 SONET/SDH Transceiver
XRT91L80IB-F		OC-48/STM-16 SONET/SDH Transceiver (2.488/2.666 Gbps)
XRT91L82IB-F		2.488/2.666Gbps STS-48/STM-16 SONET/SDH Transceiver

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