Failures by Design

By Jose Ramon Novoa, Future Electronics Spain

Cooperation between designers and their manufacturing colleagues is the key to making products that are ‘right first time.’ This collaboration ensures that the designer selects the right components, board layout and test strategy to ensure both high output and impressive yield on the factory floor.

READ THIS TO LEARN ABOUT How design engineers can cooperate with manufacturing engineers Technologies such as boundary scan that aid efficient manufacturing test How Future Electronics can support a ‘design for a manufacturing’ approach

While design for manufacture has come a long way from the days when prototypes were ‘thrown over the wall’ into production, there is still much more to be done. And there is a huge incentive to get it right. In today’s ultra competitive market, the product that can be manufactured and tested in a cost effective and timely manner – while maintaining high yields – will reach the consumer sooner and reap greater profits.

Lack of due consideration to Design for Manufacture (DFM) and Design for Test (DFT) can mean poorly assembled and insufficiently tested products reaching the customer. This inevitably leads to a high field failure rate, expensive recalls and damage to a company’s reputation.

The key to successful DFM and DFT is to include manufacturing engineers early in the design process and to understand their problems with issues such as component obsolescence. Similarly, the test department often suffers from insufficient test coverage due to the designer’s lack of foresight when moving the product from the research and development (R&D) laboratory to the factory.

In designers’ defense, they face tougher challenges than ever before, in making their products factory friendly. Smaller boards with finer pitch components and more densely packed interconnects can make it very difficult to add test access points.

Fortunately, test and component vendors have been working hard to resolve many of these issues. For example, suppliers have eased the move to Restriction of Hazardous Substances (RoHS)-compliant products by offering services such as Bill-of-Material (BOM) audits.

And designers can take advantage of functional test techniques such as Built-in Self Test (BIST) and boundary scan (also named JTAG and based on the IEEE 1149.1 standard) to dramatically improve test coverage. Moreover, forward thinking manufacturers such as National Semiconductor are helping by incorporating BIST and boundary scan directly into their components.

 

Building in Quality

Designing a product with due consideration to test throughout its life will improve the product’s total quality. But in the R&D lab, long term test considerations are often neglected in the rush to meet project deadlines.

While a designer continually debugs and analyzes his product throughout the development cycle, the lab’s test regimes will not stand up to the rigors of a production environment that has as its top priority maximizing output. Functional ‘go/no go’ tests are substituted for detailed tests using oscilloscopes and logic analyzers.

It is very important that these functional tests fully exercise the product, otherwise its integrity cannot be guaranteed. These test procedures should be continually improved using feedback from factory and field failures to enhance coverage and improve test yields.

However, it is important to realize that comprehensive test coverage cannot compensate for sub-standard manufacturing. In fact, a well regulated manufacturing process allied to a test system with reasonable coverage is better than a poorly controlled process that relies on comprehensive test coverage to pick up faulty products.

Consider a simple example: a manufacturing facility with 90% manufacturing yield and fault coverage of 99.99% will allow one faulty product into the field per hundred thousand. That is the same as a system with a 99.99% manufacturing yield with 90% fault coverage. But the cost of repair of a faulty product at test is ten times lower than at the assembly stage. So it is always better to get it right in production.

 

Aiding Production

The designer can help his manufacturing colleague by understanding his challenges. A good example is RoHS legislation. The designer must specify RoHS-compliant components throughout, because just one non-compliant chip will cause the product to fail to meet the legislation, and even worse, can contaminate the whole soldering process.

Unfortunately, component suppliers have taken different views regarding part numbering, which can cause confusion on the factory floor. Some have retained the same part number for Pb-inclusive and Pb-free components, differentiating them only with a date code. Others have retained the original part number for the Pb-inclusive version and applied a new number to the Pb-free item.

The good news is that Future Electronics can supply comprehensive documentation on a supplier’s RoHS strategy and specifications to the designer. In addition, Future can help with component labeling systems and support the transition to RoHS-compliance. Electronic components have a limited market life, and sooner or later the manufacturer makes the device obsolete. Consequently, designers need to take into account the status of the devices they are using, matching the likely component lifetime with the planned lifetime of their design.

Again, distributors are the best source of information on this, as they maintain direct contact with the manufacturers. Future Electronics informs buyers of impending end-of-life notices and offers alternatives or ‘last time buy’ information.

Nonetheless, designers should always consider second sources from the earliest stages of the design, approving alternatives with full part numbers and minimum order quantities.

Designers should also assist their manufacturing colleagues with the use of in-system programmable devices. For example, the programming pins for these types of devices should be easily accessible and not connected to loads such as large capacitors. This is straightforward if it is considered early during PCB layout, or even at the pin assignment stage.

 

Improving Test

During manufacturing test, two concepts are important: observability and controllability. Observability is a measure of the ease with which circuit signals can be observed at the PCB or silicon level. Controllability is a measure of the ease with which test signals can be applied at the PCB or silicon level.

The more complex and densely packed a system is, the more difficult it is to optimize observability and controllability because it is harder to get access to test points.

To overcome this difficulty, several new test techniques have been introduced to increase test coverage in complex products. These are:

• Physical and functional partitioning
• Increasing effective coverage of existing test points
• BIST
• Structured test systems

Functional partitioning isolates different functions of a circuit in functionally independent and complete modules and can be used for hardware and software. For example, even though the clock path connects to most parts of the circuit (and can be controlled by some parts), it is important to isolate it in order to define problems that may be directly due to clock malfunction. The same technique is applicable to other circuit elements such as power supply circuitry and memory functions.

A second partitioning technique is physical partitioning. For example, it is good practice to group analog circuitry in a different area from digital devices, primarily to avoid interference, but also to apply a different test procedure to each part. CAD tools used to generate PCB schematics can sometimes conflict with this requirement, as their primary function is usually to minimize PCB footprint and net lengths. In doing so, they can mix analog and digital circuitry, and high- and low-voltage paths. Designers will need to take note of this when reviewing the output from their CAD tools.

As electronic designs make increasing use of finepitch devices, or those with hidden leads such as Ball Grid Arrays (BGA), and PCBs with many layers, many circuit nets are inaccessible to the probes of bed-of-nails testers. Consequently, the test points that are available must offer maximum observability and controllability. Passive test points provide analog signals for oscilloscopes, or digital signals for digital analyzers. Active test points allow input signals to increase the controllability of the circuit, such as initializing digital circuits, bypassing internal clock sources with customer defined clock signals, or defining feedback loops.

Designers are the best people to define these points because they know the critical nets that affect most of the design. There are programs that can simulate the complete board and its failure coverage; these are especially useful if a designer has simulation models for all devices on the board. However, fault coverage can usually be improved by manual intervention and heuristic techniques.

BIST is primarily based on signature analysis and consists of self generation of many pseudo-random test vectors that generate a signature at the output of the tested device. For a digital circuit with known initial conditions, the generated signature should be unique.

BIST is not only useful for auto testing ASICs or complex blocks, but also transmission lines that otherwise would be very difficult to test. An example is an LVDS transmission line that due to its differential and high-speed characteristics is difficult to check using structural test procedures. However, by using BIST the emitter can generate a long test pattern that is sent to a receiver, which then compares received values against expected ones. The receiver then indicates any errors. This system tests the emitter, receiver, connectors and cables.

BIST is not widely used in board designs, as there is no standard procedure for integration into larger systems. It is mainly used to enhance testability of single ICs prior to board assembly. However, thanks to the recent introduction of structured testing techniques, it is now possible to add BIST capabilities to assembled boards, for in-field testing, using the same test vectors employed during factory test.

 

 

Structured Test Using Boundary Scan

A structured test is one that closely defines the methodology, allowing different designs to be tested with the same equipment and procedures. The most widely used structured test is based on boundary scan. Boundary scan provides a means to test connections between ICs on an assembled board without using physical test probes, via a Test Access Port (TAP). The technique adds a boundary scan cell that includes a multiplexer and latches to each pin on the device (see Figure 1). Boundary scan cells in a device can capture data from pin or core logic signals, or input data via the pins. The captured data is then serially shifted out and compared to the expected results.

The method is controlled via a serial data path called the ‘scan path’ or ‘scan chain.’ By allowing direct access to nets, boundary scan eliminates the need for a large number of test vectors, which are typically required to initialize sequential logic. Tens or hundreds of vectors may be sufficient to conduct a test that had previously required thousands of vectors.

Potential benefits of boundary scan are shorter test times, higher test coverage, increased diagnostic capability and lower capital equipment cost. A further advantage is that it can be used for programming devices after manufacturing, or for emulation with the final board during the software design phase. Moreover, boundary scan remains accessible for test in the field for maintenance purposes, verification and software updates.

Unfortunately, many designs include few or no devices with boundary scan capability. Fairchild Semiconductor, however, offers its SCAN family of logic devices such as the SCAN18373. This is a transparent latch with a three-state output, and includes JTAG boundary scan. The device also provides JTAG functionality to the nets connected to it and if a designer needs a transceiver, flip-flop or line driver, there are other members of this family that will offer JTAG functionality to these functions.

While boundary scan chains can be cascaded, it makes sense to partition chains for programmable logic, microprocessors and ASICs in the same way as analog and digital elements are partitioned during traditional test. This allows independent control of each area.

National Semiconductor supplies the SCANSTA111 for chain partition. The SCANSTA111 extends the test bus into a multi-drop test-bus environment. The advantage of a multi-drop approach over a single serial scan chain is improved test throughput and the ability to remove a board from a multi-board system while retaining test access to the remaining modules. An improved version of the SCANSTA111 is the SCANSTA112, which supports up to seven local boundary scan chains that can be accessed individually or combined serially.

In addition, the SCANSTA101 converts parallel commands to serial JTAG vectors that can be introduced in the field to test the boards using the same procedures as in manufacturing, permitting in-field test and reprogramming for systems with limited access.

Several high speed LVDS products from National Semiconductor, such as the SCAN921023 or SCAN921224, include BIST to verify at high speed not only the boards, but also the LVDS transmission lines communicating at full speed.

 

Cooperation is Key

While education, supplier initiatives and innovative test techniques such as BIST and boundary scan have significantly eased the designer’s DFM and DFT responsibilities, it is internal communication that is by far the best tool.

It is amazing what a designer can learn from simply touring the factory floor and understanding the challenges faced by manufacturing. This one action can lead a designer to select, for example, one component over another because it has a more printer friendly profile, or because its packaging is able to withstand higher reflow thermal profiles.

Manufacturing engineers could also ease the designer’s life by reviewing proposed BOMs, PCB profiles and test regimes to offer feedback and advice. Finally, do not forget your component supplier. Future Electronics employs talented engineers who are willing to offer advice on DFM and DFT founded on their vast experience dealing with hundreds of customers.