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XRT86VL38 – Eight Channel T1/E1/J1 Framer and Line Interface Combination

The device is offered in eight and four channel versions incorporating a T1/E1 (1.544Mbit/s or 2.048 Mbt/s) framer and a LIU per channel. Each of the framers has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required. Each framer also contains a transmit and overhead data input port, which permits data line terminal equipment direct access to the out bound T1/E1/J1 frames. The device has a flexible microprocessor interface for easy configuration, control and status monitoring. Furthermore, the device supports Channel Associated Signaling (CAS), Common Channel Signaling (CCS), supports ISDN primary Rate Interface (ISDN PRI) signaling and has three integrated HDLC controllers with two 96-byte transmit HDLC buffers and two 96-byte receive buffers per channel. In addition, the XRT86L38 and XRT86L34 include a PRBS, QRSS and network loop code generator/receiver. It also detects OOF, LOF, LOS errors and COFA conditions.

 

FEATURES Eight and four channel Independent, Full Duplex DS1 Tx and Rx Framers and LIUs Interfaces with leading microprocessors: Intel, Motorola, MIPS, Power PC Three integrated HDLC controllers with two 96-byte transmit HDLC buffers and two 96-byte receive buffers per channel

APPLICATIONS Channel Service Units (CSUs) Digital access cross connect systems (DACs) Wireless base stations Voice over packet gateways Framer relay switches and access devices (FRADS)

 

 

XRT86SH328 - Integrated 28 Channel T1/E1 LIU/Framer, VT/TU Mapper and M13 Multiplexer

The XRT86SH328 is an integrated VT/TU Mapper with 28 port T1/E1 line interface units. The XRT86SH328 contains integrated DS1/E1/J1 framers for performance monitoring.

The XRT86SH328 processes the section, line and path overhead in the SONET/SDH data stream. The processing of path overhead bytes within the STS-1s or TUG-3s include 64-bytes (of buffer) for storing the (Section Trace and Path Trace) messages. Path overhead bytes can be accessed either by on-chip registers or a serial output port.

Each of the 28 T1 or E1 channels use an internal de-synchronizer circuit with an internal pointer leak algorithm. This removes the jitter due to mapping and pointer adjustments from the T1 or E1 signals that are de-mapped from the incoming SONET/SDH data stream. These de-synchronizer circuits do not need any external clock references for its operation.

The transmit blocks permit flexible insertion of TOH and POH bytes via both hardware and software control.

The receive blocks receive a SONET STS-1 signals or an SDH STM-1 signal and performs the necessary transport and path overhead processing.

A PRBS pattern generator and receiver is implemented within each of the 28 T1/E1 channels in order to implement and measure bit error performance.

A general purpose microprocessor interface is included for control, configuration and monitoring.

 

FEATURES Provides mapping of up to 28 T1 streams as asynchronous VT1.5 into an STS-1 SPE or TU-11 tributary unit into an STM-1/VC-3 or TUG-3 from STM-1/VC-4 Supports 28 T1 streams M13 multiplexed into a serial DS3 Supports 21 E1 streams M13 multiplexed into a serial DS3 (compliant with ITU-T G.747) 28 T1 Streams M13 multiplexed into a DS3 and DS3 is asynchronously mapped into STS-1 21 E1 Streams M13 multiplexed into a DS3 (ITU-T G.747) and DS3 is asynchronously mapped into STS-1 Supports 21 E1 mapped as asynchronous VT2 into an STS-1 SPE or TU-12 tributary units into STM-1/VC-3 or TUG-3 from a STM-1/VC-4 Supports TU cross mapping function TU-12/VC-11/T1 Supports mixed mapping of VT-G/VT1.5 and VT-G/VT2 Supports mixed mapping of TUG-2/TU-11 and TUG-2/TU-12 28 VT1.5/TU-11 or 21 VT-2/TU-12 tributaries can be passed as transparent between SONET/SDH telecom bus on the line side and clock and data on the system side Supports unframed T1/E1 signals Supports DS1/E1 performance monitoring in both egress and ingress direction VC-11/VC-12 tandem connection monitoring support Complies with the Category I Intrinsic Jitter Requirements for DS1 signals being de-mapped from SONET, per Telcordia GR-253-CORE Complies with the "Mapping Jitter Generation Specification" for DS1 and E1 signals being de-mapped from SDH, per ITU-T G.783 Complies with the "Combined Jitter Generation Specification" for DS1 and E1 signals being de-mapped from SDH, per ITU-T G.783 Line and facility loop-backs Each of the 28 T1/E1 channels includes a PRBS generator and receiver Each of the 28 VT mapper blocks are capable of generating BIP-2 and REI errors upon software command (for diagnostic purposes) The Transmit and Receive DS3 framer blocks support both the M13(M23) and the C-bit Parity Framing formats Integrated 28 T1/E1/J1 short haul line interface units IEEE 1149.1 Standard Boundary Scan Low Power: 1.8V power supply for core logic; 3.3V power supply for I/O General purpose microprocessor interface

APPLICATIONS Channelized and unchannelized DS3 applications T1/E1 terminals SONET/SDH ADM

 

 

XRT83SH314 – 14 Channel T1/E1/J1 Short Haul Line Interface Unit

XRT83L314 - 14 Channel T1/E1/J1 Long Haul/Short Haul Line Interface Unit

The XRT83SH314 is a fully integrated 14 channel short haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1 or J1 mode independently on a per channel basis with minimum external components.

The LIU features are programmed through a standard microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays.

The XRT83L314 is a fully integrated 14-channel long-haul and short-haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays.

The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and has five output clock references that can be used for external timing (8 kHz, 1.544 MHz, 2.048 MHz, nxT1/J1, nxE1).

Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS/PRBS generation/detection, TAOS, DMO and diagnostic loop back modes.

 

FEATURES Fully integrated 14 channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications T1/E1/J1 short haul and clock rate are per port selectable through software without changing components Internal Impedance matching on both receive and transmit for 75Ω (E1), 100Ω (T1), 110Ω (J1), and 120Ω (E1) applications are per port selectable through software without changing components Power down on a per channel basis with independent receive and transmit selection Five pre-programmed transmit pulse settings for T1 short haul applications per channel On-chip transmit short circuit protection and limiting protects line drivers from damage on a per channel basis Selectable Crystal-Less digital jitter attenuators (JA) with 32-bit or 64-bit FIFO for the receive or transmit path On-chip frequency multiplier generates T1 or E1 master clocks from a variety of external clock sources (8, 16, 56, 64, 128, 256kHz and 1X, 2X, 4X, 8X T1 or E1) Driver failure monitor output (DMO) alerts of possible system or external component problems Transmit outputs and receive inputs may be "High" impedance for protection or redundancy applications on a per channel basis Support for automatic protection switching 1:1 and 1+1 protection without relays Receive monitor mode handles 0 to 29dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1 Loss of signal (RLOS) according to ITU-T G.775/ETS300233 (E1) and ANSI T1.403 (T1/J1) Programmable data stream muting upon RLOS detection On-chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel On-chip digital clock recovery circuit for high input jitter tolerance QRSS/PRBS pattern generator and detection for testing and monitoring Error and bipolar violation insertion and detection Transmit all ones (TAOS) generators and detectors Supports local analog, remote, digital and dual loop back modes TBD per channel low power dissipation (50% density) TBD per channel maximum power dissipation (100% density) Single 3.3V supply operation (3V to 5V I/O tolerant) 304-Pin TBGA package -40°C to +85°C temperature range Supports gapped clocks for mapper/multiplexer applications

APPLICATIONS T1 Digital Cross Connects (DSX-1) ISDN primary rate interface CSU/DSU E1/T1/J1 interface T1/E1/J1 LAN/WAN routers Public switching systems and PBX interfaces T1/E1/J1 multiplexer and channel banks Integrated multi-service access platforms (IMAPs) Integrated access devices (IADs) Inverse multiplexing for ATM (IMA) Wireless base stations

 

 

XRT83SH38 – 8 Channel T1/E1/J1 Short Haul Line Interface Unit

XRT83L38 – 8 Channel T1/E1/J1 Long Haul/Short Haul Line Interface Unit

The XRT83SH38 is a fully integrated 8 channel short haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode with minimum external components. The LIU features are programmed through a standard microprocessor interface, serial interface (BGA package only) or controlled through Hardware mode. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays.

The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and outputs a clock reference of the line rate chosen.

Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS generation/detection, TAOS, DMO, and diagnostic loop back modes.

 

FEATURES (XRT83SH38) Fully integrated eight channel short haul transceivers for E1, T1 or J1 applications Programmable Transmit Pulse Shaper for E1, T1 or J1 short haul interfaces Five fixed transmit pulse settings for T1 short haul applications Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for E1 and 0 to 3dB of cable attenuation for T1 modes Internal impedance matching for 75Ω, 100Ω, 110Ω and 120Ω Tri-state transmit output and receive input capability for redundancy applications Provides high impedance for Tx and Rx during power off Transmit return loss meets or exceeds ETSI 300-166 standard On-chip digital clock recovery circuit for high input jitter tolerance Crystal-less digital jitter attenuator with 32-bit or 64- bit FIFO selectable either in transmit or receive path On-chip frequency multiplier generates T1 or E1 master clocks from variety of external clock sources High receiver interference immunity On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO) Receive loss of signal (RLOS) output On-chip HDB3/B8ZS/AMI encoder/decoder functions QRSS pattern generator and detection for testing and monitoring Error and Bipolar Violation Insertion and Detection Transmit All Ones (TAOS) generators and detectors Supports Local Analog, Remote, Digital and Dual Loop Back Modes Meets or exceeds T1 and E1 short haul network access specifications in ITU G.703, G.775, G.736, and G.823; TR-TSY-000499; ANSI T1.403 and T1.408; ETSI 300-166 and AT&T Pub 62411 Supports both hardware and host (parallel microprocessor or serial) interface for programming JTAG support Programmable interrupt Low power dissipation Logic inputs accept either 3.3V or 5V levels Single 3.3V supply operation 225 ball BGA package -40°C to +85°C temperature range

APPLICATIONS (XRT83SH38) T1 Digital Cross Connects (DSX-1) ISDN primary rate interface CSU/DSU E1/T1/J1 interface T1/E1/J1 LAN/WAN routers Public switching systems and PBX interfaces T1/E1/J1 multiplexer and channel banks

 

 

FEATURES (XRT83L38) On-chip frequency multiplier Programmable Transmit Pulse Generator Supports host or hardware modes Compliant with leading industry standards Interfaces seamlessly to Exar framer products

APPLICATIONS (XRT83L38) Multi-service Provisioning Platforms (MSPP) Integrated access devices Routers Frame relay access devices Wireless base stations

 

 

 Featured Products

Part Number		Description	Data Sheet	App. Notes
XRT83L314IB-F		14 Channel T1/E1/J1 Long Haul/Short Haul Line Interface Unit
XRT83L38IV-F		Channel T1/E1/J1 Long Haul/Short Haul Line Interface Unit
XRT83SH314IB		14 Channel T1/E1/J1 Short Haul Line Interface Unit
XRT83SH38IB-F		8 Channel T1/E1/J1 Short Haul Line Interface Unit
XRT86SH328IB-F		Integrated 28 Channel T1/E1 LIU/Framer, VT/TU Mapper and M13 Multiplexer
XRT86VL38IB484-F		8 Channel T1/E1/J1 Framer and Line Interface Combination

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